The present invention relates to a semiconductor device and, more particularly, to a technique applicable to semiconductor devices having transistors and wiring lines.
There are semiconductor devices having power control transistors. An example of such semiconductor devices is disclosed in Japanese Unexamined Patent Application Publication No. 2013-201242 (patent document 1). According to the patent document 1, in a semiconductor device including compound semiconductor layers, plural transistors are arranged in parallel with each transistor having a drain electrode and a source electrode extending in opposite directions. The drain electrodes and the source electrodes of the transistors are coupled to a single drain line and a single source line, respectively. The drain line and the source line extend in the direction in which the transistors are arranged.
The semiconductor device disclosed in the patent document 1 also includes diodes which are arranged along the transistors. The anode electrodes of the diodes extend in the same direction as the drain electrodes of the transistors and are coupled to the drain line. The cathode electrodes of the diodes extend in the same direction as the source electrodes of the transistors and are coupled to the cathode line. The source line and the cathode line are separated from each other, but they are linearly aligned.